Effect of Multicycle Intructions on the Integer Performance of the Dynamixcally Trace Scheduled VLIW Architecture
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چکیده
Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction level parallelism (ILP) with backward code compatibility. This paper presents the effect of multicycle instructions on the performance of a DTSVLIW architecture running the SPECint95 benchmarks.
منابع مشابه
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تاریخ انتشار 1999